Nowadays, integrated circuits (ICs) routinely comprise patterned metallization layers for interconnecting circuit elements, e.g. transistor terminals in the substrate or to provide external access, e.g. bond pads, to the circuit elements that are embedded in the semiconductor device. Typically, the metallization layers are formed by stacking and patterning dielectric layers and metal layers to obtain the required interconnections. The dielectric and metal layers themselves may contain sub-layers. The dielectric layers typically comprise vias to conductively connect metal portions in the different metal layers with each other.
Rigorous testing of the ICs, e.g. when they are still part of a wafer, takes place to ensure that the IC operates correctly, e.g. is free of manufacturing defects. This is important because the IC may be integrated into an electronic device, where the failure of the IC in the electronic device would most likely cause the electronic device to exhibit faulty behavior. For this reason, significant efforts are made to ensure that defective ICs are removed from a batch of manufactured ICs to avoid field returns of electronic devices containing such ICs as much as possible. Field returns inconvenience the customer, and can lead to a loss of business because of the customer losing faith in the product. Nevertheless, it is very difficult to capture all defective ICs such that it cannot be avoided that some defective ICs enter the market, e.g. inside an electronic device. On the other hand, a returned faulty electronic device may have entered the market functioning correctly, where it is possible that the fault has developed through misuse of the semiconductor device, e.g. by the customer accidentally submerging the device in water. Obviously, in such a case, the manufacturer cannot be held responsible for the failure of the device.
It is difficult to establish why a semiconductor device returned from the field has failed. Re-engineering the device to determine the cause of failure is not always successful and is cost-prohibitive for single devices. U.S. Pat. No. 4,057,823 discloses a structure for a relative humidity monitor which can be built into an integrated circuit chip. A small area on a silicon chip is made porous by anodic etching. This region is then oxidized and a metal counter electrode is deposited over part of the porous area. Due to the relatively large surface area in the dielectric under the counter electrode and the openness of the structure, ambient moisture can quickly diffuse into the dielectric under the electrode and adsorb onto the silicon dioxide surface, such that changes in ambient humidity will be reflected by measurable changes in capacitance or conductance of the device.
A drawback of such a moisture sensor is that in other to determine if an electronic device returned from the field has been subjected to excess moisture, the sensor must be continuously monitored during the operational life of the electronic device and its measurements, or at least measurements exceeding a predefined threshold, stored for future read-out. This is an impractical solution.